DMATP: A Design Method and Architecture of TU Parallel Processing for 4K HEVC Hardware Encoder

This paper proposes design method and architecture of parallel processing hardware for Transform Units in High Efficiency Video Coding (HEVC). HEVC is the next generation video coding standard which is expected to be used for high resolution broadcasting such as 4K UltraHD. Since HEVC introduces higher complexities and dependencies than previous standard H.264/AVC, hardware designers have to find and utilize parallelism in HEVC to realize strict real-time encoding performance especially for broadcasting purpose. We propose design method to find appropriate parallelism considering both HEVC algorithm and hardware resources focusing on the Transform Units processing, and propose architecture to bring the parallelism efficiently. With the architecture, we got a prospect of realizing 4K HEVC encoder.